TEM study of iridium silicide contact layers for Low Schottky Barrier MOSFETs

Adam Łaszcz 1Jerzy Kątcki 1Jacek Ratajczak 1Andrzej Czerwinski 1Nicolas Breil 2,3Guilhem Larrieu 2Emmanuel Dubois 2

1. Institute of Electron Technology (ITE), al. Lotników 32/46, Warszawa 02-668, Poland
2. IEMN/ISEN, UMRS CNRS 8520, Avenue Poincare, BP69, Villeneuve d'Ascq 59652, France
3. STMicroelectronics, 850 rue Jean Monnet, Crolles CEDEX 38926, France

Abstract

An influence of annealing temperatures on the iridium silicide nanolayer formation in reaction between 15 nm thick Ir metallisation and Si substrate during annealing by the rapid-thermal-annealing (RTA) process for 120 s, was analysed using the transmission electron microscopy (TEM). The silicide layers are used as source and drain contacts for a novel technology of Low Schottky Barrier MOSFETs on SOI. The high quality of the silicide/Si interface and of the silicide structure is essential for the electrical properties of the device. The studies enabled the determination of the silicide layer thickness and morphology, as well as the silicide/Si interface roughness. Annealing of the Ir/Si structure at 300 and 400 °C caused a formation of an amorphous iridium silicide layer between Ir and Si layers, which thickness is about 5 and 7 nm, respectively, and the Ir/Ir-Si/Si interfaces are smooth. At 500 °C the whole Ir layer completely reacted with Si, forming about 30 nm thick crystalline IrSix layer. Irregular grains are visible in this layer. The IrSix/Si interface is slightly rough. When the annealing temperature increases the reaction depends more on the diffusion of Si atoms into the polycrystalline Ir layer than on the Ir diffusion into the Si substrate. The diffusion of Si atoms is already predominant at 500 °C. The diffraction analysis showed that the most stable phase at 500°C is IrSi.

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Presentation: Poster at E-MRS Fall Meeting 2006, Symposium I, by Adam Łaszcz
See On-line Journal of E-MRS Fall Meeting 2006

Submitted: 2006-05-12 11:55
Revised:   2009-06-07 00:44
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